By Himanshu Bhatnagar
Advanced ASIC Chip Synthesis: utilizing Synopsys® Design Compiler® actual Compiler® and PrimeTime®, Second Edition describes the complicated innovations and strategies used in the direction of ASIC chip synthesis, actual synthesis, formal verification and static timing research, utilizing the Synopsys suite of instruments. furthermore, the complete ASIC layout circulate technique distinct for VDSM (Very-Deep-Sub-Micron) applied sciences is roofed intimately.
The emphasis of this publication is on real-time software of Synopsys instruments, used to strive against quite a few difficulties noticeable at VDSM geometries. Readers can be uncovered to an efficient layout technique for dealing with complicated, sub-micron ASIC designs. value is put on HDL coding types, synthesis and optimization, dynamic simulation, formal verification, DFT experiment insertion, hyperlinks to format, actual synthesis, and static timing research. At every one step, difficulties comparable to every part of the layout stream are pointed out, with strategies and work-around defined intimately. additionally, an important matters similar to structure, consisting of clock tree synthesis and back-end integration (links to structure) also are mentioned at size. additionally, the ebook comprises in-depth discussions at the foundation of Synopsys know-how libraries and HDL coding kinds, detailed in the direction of optimum synthesis answer.
goal audiences for this ebook are training ASIC layout engineers and masters point scholars venture complicated VLSI classes on ASIC chip layout and DFT ideas.
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Additional info for Advanced ASIC Chip Synthesis Using Synopsys Tools
This helps the reader correlate the theoretical concepts with its practical application. In order to describe both the traditional and the physical compiler based flows, all scripts related to the former are maintained (the commands have been changed to the Tcl format). A separate section based on the Physical Compiler (or PhyC) flow has been added. This provides the users the ability to choose whichever flow best suits their design needs. 20 Chapter 2 Although, the previous chapter stressed skipping the gate-level simulation in favor of formal verification techniques, many designers are reluctant to forego the former step.
Pre-layout static timing analysis using PrimeTime (delay numbers based on placement rather than wire-load models). 5. Formal verification of the design. RTL against the synthesized netlist, using Formality. 6. Port the netlist and the placement information over to the layout tool. 7. Insert clock tree in the design using the layout tool. 8. Formal verification between clock tree inserted netlist and the original scan inserted netlist. 9. Perform detailed routing using the layout tool. 10. Extract real timing delays from the detailed routed design.
Similar to post-placement, the post-route timing analysis uses the same commands, except that this time the actual delays are back annotated to the design. Predominantly, the timing of the design is dependent upon clock latency and skew. It is therefore prudent to perform the clock skew analysis before attempting to analyze the whole design. A useful Tcl script is provided by Synopsys through their on-line support on the web, called SolvNET. You may download this script and run the analysis before proceeding.