By P. Chu
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Extra info for Advances in Solid-State Circuits Technologies
IEEE Trans. Circuits Syst. I, Fundam. , vol. 45, no. 3, 1998, pp. 300–304. ; Jaime Ramirez-Angulo; Lopez-Martin, A. & Sanchez-Sinencio, E. (2004). A fully parallel CMOS analog median filter. IEEE Trans. Circuits Syst. II, vol. 51, March 2004, pp. 116 – 123. He, Y. & Sanchez-Sinencio, E. (1993). Min-net winner-take-all CMOS implementation. Electron. , vol. 29, no. 14, 1993, pp. 1237–1239. ; Maeda, A. & Yazawa, N. (1990). An 8-bit 20-MS/s CMOS A/D converter with 50-mW power consumption. IEEE J. Solid-State Circuits, vol.
VC Iout M2 M3 IC Vin M1 Fig. 3. 3 Transconductor using source degeneration A simple differential transconductor is shown in Fig. 4(a). Assuming that M1 and M2 are in saturation and perfectly matched, the drain current is given by ID = β 2 (VGS − VT )2 (11) 31 Transconductor The transfer characteristic using (5) is given by βVi2 I out = I out 1 − I out 2 = 2 βI SS Vi 1 − 8 I SS = 2 βI SS Vi 1 − Vi2 4(VGS − VT ) (12) , where Vi = (Vin1 −Vin2) If VGS is large enough, the higher linearity can be achieved.
In order to verify the performance of the proposed transconductor, we define transconductance error (equation 39) as the linearity of the transconductance’s output current. 8V. TE(%) = Gm (Vid ) − Gm (0 ) * 100 Gm (0 ) (39) 37 Transconductor Fig. 9. V-I transfer characteristic Fig. 10. 7V In Fig. 11. it shows the drain-source voltage of the input transistors M1 and M2, VDS1 and VDS2, changes with the input voltage. Within ±1V input voltage, VDS1 and VDS2 are very small. According to equation (40), VDS1 and VDS2 are too small such that transistors M1 and M2 can be set in triode region.